An integrated circuit contains various semiconductor devices and a plurality of conducting metal paths that provide electrical power to the semiconductor devices and allow these semiconductor devices to share and exchange information. Within an integrated circuit, metal layers are stacked on top of one another using intermetal or interlayer dielectric layers that insulate the metal layers from each other. Metal layers typically occupy etched pathways in the interlayer dielectric. Normally, each metal layer must form an electrical contact to at least one additional metal layer or conductive layer. Such electrical contact is achieved by etching a hole in the interlayer dielectric that separates the metal layers or a metal layer and a doped substrate region, and filling the resulting via with a metal (plug) to create a vertical interconnect structure. A “via” normally refers to any micro-feature such as a hole, line or other similar feature formed within a dielectric layer that provides an electrical connection through the dielectric layer to a conductive layer underlying the dielectric layer. Similarly, micro-features containing metal layers connecting two or more vias are normally referred to as trenches.
Tungsten (W) plug metallization is widely used for vertical interconnect structures of various metal layers in integrated circuit fabrication. The scaling of interconnect structures, including contact size, results in an increase in contact resistivity. Replacing the conventional W plug with a lower contact resistivity metal such as copper (Cu) provides significant gains in switching delay (RC-delay) and power consumption. Furthermore, Cu plugs alleviate the rapid rise in resistance as W contacts scale below about 70 nm (nm=10−9 m) in diameter. Metal plugs are surrounded by barrier films that separate the metal plugs from dielectric materials and other materials in the semiconductor device. Cu cannot be put in direct contact with dielectric materials since Cu has poor adhesion to the dielectric materials and Cu is known to easily diffuse into common integrated circuit materials such as silicon and dielectric materials where Cu is a mid-bandgap impurity. Furthermore, oxygen can diffuse from an oxygen-containing dielectric material into Cu, thereby decreasing the electrical conductivity of the Cu metal. Therefore, a diffusion barrier material is formed on dielectric materials and other materials in the integrated circuits to surround the Cu and prevent diffusion of the Cu into the integrated circuit materials. The diffusion barrier material for Cu metallization usually includes a Ta-containing material, for example a TaN/Ta bilayer.
One area of concern when using Cu and W plugs is the contact resistivity at the bottom of a via. The presence of contaminants such as oxygen in the Ta-containing material can result in high contact resistivity and in weak adhesion between Ta-containing material and other materials at the bottom of the via. Thus, new processing methods are needed for improving contact resistivity and film properties for contact structures containing Cu.